(this page is still under construction, sorry for the inconvenience)
Our goal is to produce a highly secure software hardware computing platform, featuring:
- A flexible approach where both software and hardware security rules can be updated dynamically in a per application basis or in order to update security rules when new threats are discovered.
- A large set of security rules with variable tag sizes and formats depending on the requirements.
- A persistent tag management feature relying on OS support.
- A cooperation mechanism between software static analysis and hardware DIFC to be able to monitor different types of information flow and so to address both confidentiality and integrity.
- A complete prototype of the system on a SoC platform that combines an ASIC main processor (ARM) coupled with an FPGA, such as Xilinx Zynq devices.
- CentraleSupélec/INRIA, CIDRE research team.
- CentraleSupélec/IETR, SCEE research team.
- Lab-STICC laboratory, University of South Brittany.
- Pascal Cotret, email@example.com.
- Guillaume Hiet, firstname.lastname@example.org.
- Guy Gogniat, email@example.com.